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[AK4621] ms1258-e-01 2011/01 - 1 - general description the AK4621 is a high performance 24- bit codec that supports up to 192khz recording and playback. the on-board analog-to-digital converter has a hi gh dynamic range due to akm ?s enhanced dual-bit architecture. the dac utilizes akm?s advanced multi-bit architecture that achieves low out-of-band noise and high jitter tolerance through the use of switched capacit or filter (scf) technology. the AK4621 is ideal for pro audio sound cards, digital audio wor kstations, dvd-r, hard disk, cd-r recording/playback systems, and musical instrument recording. features 24-bit 2-channel adc - full differential inputs - selectable digital filter 1. adc sharp roll off filter (gd=39/fs) passband: 0 ~ 21.8khz (@fs=48khz) stopband attenuation: 100db 2. adc short delay sharp roll off filter (gd=14/fs) passband: 0 ~ 21.7khz (@fs=48khz) stopband attenuation: 80db - s/(n+d): 102db - s/n: 115db - digital high-pass filter for offset cancellation - overflow flag - audio interface format: msb justified or i 2 s 24-bit 2-channel dac - selectable digital filter 1. dac sharp roll off filter (gd=27/fs) passband: 0 ~ 21.8khz (@fs=48khz) stopband attenuation: 70db 2. dac slow roll off filter (gd=27/fs) passband: 0 ~ 8.9khz (@fs=48khz) stopband attenuation: 73db 3. dac short delay sharp roll off filter (gd=7/fs) passband: 0 ~ 21.8khz (@fs=48khz) stopband attenuation: 70db - switched-cap low pass filter - differential outputs - s/(n+d): 100db - s/n: 115db - de-emphasis for 32khz, 44.1khz, 48khz sampling - output digital attenuator: 0db ~ ? 72db, linear 256 + 16steps - zero detection function - audio interface format: msb justified, lsb justified, i 2 s high jitter tolerance sampling rate: 32khz ~ 216khz p interface: 3-wire serial interface master clock: 128fs/192f s/256fs/384fs/512fs/768fs/1024fs 24-bit 192khz stereo audio codec AK4621
[AK4621] ms1258-e-01 2011/01 - 2 - power supply analog: 4.75 ~ 5.25v (typ. 5.0v) digital: 3.0 ~ 3.6v (typ. 3.3v) digital i/o: dvdd ~ 5.25v (typ. 5.0v) package: 30pin vsop ta: -10 ~ 70 c block diagram adc a inl- pdn lrck bick control register i/f vcom av dd hpf au d io interface vref dem0 a inl+ a in r - a inr+ ovfr/dzf r ovf ovfl/dzfl datt smute sdto dfs0 mclk p/s sdti dvdd vss1 tvdd vss2 cdti/ cks0 cclk/ cks1 csn/ dif dac a outl- a outl+ a outr- aoutr+ sdfil figure 1. block diagram
[AK4621] ms1258-e-01 2011/01 - 3 - ordering guide AK4621ef ? 10 +70 c 30pin vsop (0.65mm pitch) akd4621 evaluation board for AK4621 pin layout 6 5 4 3 2 1 vcom ainr+ ainl+ ainr- ainl- vref vss1 7 avdd 8 top view 10 9 p/s mclk lrck 11 bick 12 13 14 sdto sdti aoutr+ aout r - aoutl+ aoutl- vss2 dvdd tvdd sdfil dem0 pdn dfs0 csn/dif 25 26 27 28 29 30 24 23 21 22 20 19 18 17 cclk/cks1 cdti/cks0 15 ovfr/dzf r 16 ovfl/dzfl
[AK4621] ms1258-e-01 2011/01 - 4 - compatibility with ak4620b 1. function function ak4620b AK4621 max fs 216khz adc inputs single-ended di fferential differential input analog pga 0 ~ +18db 0.5db/step - - input digital att mute,-63.5db ~ 0db 0.5db/step mute,-63.5db ~ 0db 0.5db/step - adc s/(n+d) 90db 100db 102db adc dr, s/n 110db 113db 115db adc digital filter type sharp roll-off sharp roll-off short delay sharp roll-off adc digital filter sa 100db 100db 80db adc digital filter gd 43.2/fs 39/fs 14/fs dac s/(n+d) 97db (0dbfs) 100db (-1dbfs) dac dr, s/n 115db dac digital filter type sharp roll-off slow roll-off sharp roll-off slow roll-off short delay sharp roll-off dac digital filter sa 75db 72db 70db 73db 70db dac digital filter gd 28/fs 28/fs 27/fs 27/fs 7/fs output digital attenuator mute, -48db ~ 0db linear 256 steps mute, -48db ~ 0db linear 256 steps mute, -72db ~ 0db linear 16 + 256 steps dac dsd mode x - dac zero-data detection x parallel mode x x: available, -: not available 2. register (difference from ak4620b) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control slow dzfb zoe zos sdda pwvr pwad pwda 01h reset control d/p dcks dckb sdad aml amr rstad rstda 02h clock and format control dif2 dif1 dif0 cmode cks1 cks0 dfs1 dfs0 03h deem and volume c ontrol smute hprn hpln zc ei ztm1 ztm0 dem1 dem0 04h reserved iattl7 iattl6 iattl5 iattl4 iattl3 iattl2 iattl1 iattl0 05h reserved iattr7 iattr6 iattr5 iattr4 iattr3 iattr2 iattr1 iattr0 06h lch datt control dattl7 da ttl6 dattl5 dattl4 dattl3 dattl2 dattl1 dattl0 07h rch datt control dattr7 dattr6 da ttr5 dattr4 dattr3 dattr2 dattr1 dattr0 08h lch extension datt control 0 0 exte 0 eattl3 eattl2 eattl1 eattl0 09h rch extension datt control 0 0 0 0 eattr3 eattr2 eattr1 eattr0 these bits were added in the AK4621. these bits were deleted in the AK4621.
[AK4621] ms1258-e-01 2011/01 - 5 - pin/function no. pin name i/o function 1 vcom o common voltage output pin, (avdd)/2 bias voltage of adc inputs and dac outputs. 2 ainr+ i rch positive input pin 3 ainr- i rch negative input pin 4 ainl+ i lch positive input pin 5 ainl- i lch negative input pin 6 vref i voltage reference input pin, avdd used as a voltage reference by adc & dac. vref is connected externally to filtered avdd. 7 vss1 - analog ground pin 8 avdd - analog power supply pin, 4.75 5.25v 9 p/s i parallel/serial mode select pin ?l?: serial mode, ?h?: parallel mode do not change this pin during pdn pin = ?h?. 10 mclk i master clock input pin 11 lrck i input/output channel clock pin 12 bick i audio serial data clock pin 13 sdto o audio serial data output pin 14 sdti i audio serial data input pin ovfr o rch over flow flag pin (in parallel mode or when zos bit=?0? in serial mode) 15 dzfr o rch zero detection flag pin (when zos bit=?1? in serial mode) ovfl o lch over flow flag pin (in parallel mode or when zos bit=?0? in serial mode) 16 dzfl o lch zero detection flag pin (when zos bit=?1? in serial mode) cdti i control data input pin (in serial mode) 17 cks0 i master clock select pin (in parallel mode) cclk i control data clock pin (in serial mode) 18 cks1 i master clock select pin (in parallel mode) csn i chip select pin in serial mode (in serial mode) 19 dif i digital audio interface sel ect pin (in parallel mode) ?l?: 24bit msb justified, ?h?: i2s compatible 20 dfs0 i double speed sampling mode pin 21 pdn i power-down mode pin ?l?: power down reset and initialize the control register, ?h?: power up 22 dem0 i de-emphasis control pin 23 sdfil i digital filter select pin ?l?: short delay sharp roll off filter (adc ), short delay sharp roll off filter (dac) ?h?: sharp roll off filter (adc), sharp roll off filter (dac) 24 tvdd - digital i/o power supply pin, dvdd 5.25v 25 dvdd - digital power supply pin, 3.0 3.6v 26 vss2 - digital ground pin 27 aoutl- o lch negative analog output pin 28 aoutl+ o lch positive analog output pin 29 aoutr- o rch negativ e analog output pin 30 aoutr+ o rch positive analog output pin note 1. all digital input pins (p/s, mclk, lrck, bick, sdti, cdti/cks0, cclk/cks1, csn/dif, dfs0, pdn, dem0 and sdfil) must not be left floating.
[AK4621] ms1258-e-01 2011/01 - 6 - handling of unused pin the unused i/o pin must be processed appropriately as below. classification pin name setting ainl+, ainl- ainl+ pin is connected to ainl- pin. analog input ainr+, ainr- ainr+ pin is connected to ainr- pin. analog output aoutl+, aoutl-, aoutr+, aout r- these pins must be open. digital output ovfl/dzfl, ovfr/dzfr these pins must be open. absolute maximum ratings (vss1=vss2=0v; note 2, note 3 ) parameter symbol min max units power supplies: analog digital digital i/o avdd dvdd tvdd -0.3 -0.3 -0.3 6.0 6.0 6.0 v v v input current, any pin except supplies iin - 10 ma analog input voltage ( note 4 ) vina -0.3 avdd+0.3 v digital input voltage ( note 5 ) vind -0.3 tvdd+0.3 v ambient temperature (power applied) ta -10 70 c storage temperature tstg -65 150 c note 2. all voltages with respect to ground. note 3. vss1 and vss2 must be connected to the same analog ground plane. note 4. ainl+, ainl-, ainr+ and ainr- pins note 5. p/s, mclk, lrck, bick, sd ti, cdti/cks0, cclk/cks1, csn/dif, dfs0, pdn, dem0 and sdfil pins. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=0v; note 2 ) parameter symbol min typ max units power supplies ( note 6 ) analog digital digital i/o avdd dvdd tvdd 4.75 3.0 dvdd 5.0 3.3 5.0 5.25 3.6 5.25 v v v voltage reference vref 3.0 - avdd v note 2. all voltages with respect to ground. note 6: the power up sequence am ong avdd, dvdd and tvdd is not critical. warning: akm assumes no responsibility for the us age beyond the conditions in this datasheet.
[AK4621] ms1258-e-01 2011/01 - 7 - analog characteristics (ta=25 c; avdd=5v, dvdd=3.3v, tvdd=5v; vss1=vss2=0v; vref=avdd; fs=48khz; signal frequency =1khz; 24bit data; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max units adc analog input characteristics: resolution - - 24 bits input voltage ( note 7 ) 2.62 2.82 3.02 vpp fs=48khz - 13 - k fs=96khz - 13 - k input resistance fs=192khz - 13 - k fs=48khz bw=20khz -1dbfs -60dbfs 92 - 102 52 - - db db fs=96khz bw=40khz -1dbfs -60dbfs - - 101 48 - - db db s/(n+d) fs=192khz bw=40khz -1dbfs -60dbfs - - 101 48 - - db db dynamic range (-60dbfs with a-weighted) - 115 - db s/n (a-weighted) 105 115 - db interchannel isolation 90 110 - db interchannel gain mismatch - 0 0.3 db gain drift ( note 12 ) - 20 - ppm/ c power supply rejection ( note 8 ) - 50 - db dac analog output characteristics: parameter min typ max units resolution - - 24 bits dynamic characteristics fs=48khz bw=20khz ? 1dbfs ? 60dbfs 90 - 100 52 - - db db fs=96khz bw=40khz ? 1dbfs ? 60dbfs - - 97 49 - - db db s/(n+d) fs=192khz bw=40khz ? 1dbfs ? 60dbfs - - 97 49 - - db db dynamic range ( ? 60dbfs with a-weighted) ( note 9 , note 10 ) - 115 - db s/n (a-weighted) ( note 10 , note 11 ) 107 115 - db interchannel isolation (1khz) 90 110 - db dc accuracy interchannel gain mismatch - 0 0.3 db gain drift ( note 12 ) - 20 - ppm/ c output voltage ( note 13 ) 2.6 2.8 3.0 vpp load capacitance - - 25 pf load resistance ( note 14 ) 2 - - k note 7. full scale (0db) of the input voltage. vin (typ) = 2.82vpp x vref/5. note 8. psr is applied to avdd, dvdd, tvdd with 1khz, 50mvpp. vref pin is held a constant voltage. note 9. 100db at 16bit data and 114db at 20bit data. note 10. by figure 20 . external lpf circuit example 2. note 11. s/n does not depend on input bit length. note 12. the voltage on vref is held +5v externally. note 13. full scale voltage (0db). output voltage scales with the voltage of vref. aout (typ.@0db) = (aout+) - (aout-) = 5.6vpp x vref/5. note 14. for ac-load.
[AK4621] ms1258-e-01 2011/01 - 8 - parameter min typ max units power supplies power supply current normal operation (pdn pin = ?h?) avdd - 34 51 ma dvdd+tvdd (fs=48khz) (fs=96khz) (fs=192khz) - - - 11 20 27 - 30 41 ma ma ma power-down mode (pdn pin = ?l?) ( note 15 ) avdd dvdd+tvdd - - 10 10 100 100 a a note 15. all digital input pins are held tvdd or vss2.
[AK4621] ms1258-e-01 2011/01 - 9 - adc sharp roll off filter characteristics (fs=48khz) (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; normal speed mode; sdad bit = ?0?) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 16 ) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - - 22.0 22.3 24.0 21.8 - - - khz khz khz khz stopband ( note 16 ) sb 26.5 - - khz passband ripple pr - - 0.005 db stopband attenuation sa 100 - - db group delay ( note 17 ) gd - 39 - 1/fs group delay distortion gd - 0 - s adc digital filter (hpf): frequency response ( note 16 ) ? 3db ? 0.1db fr - - 1.0 6.5 - - hz hz adc sharp roll off filter characteristics (fs=96khz) (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; double speed mode; sdad bit = ?0?) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 16 ) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - - 44.1 44.5 48.0 43.7 - - - khz khz khz khz stopband ( note 16 ) sb 53.0 - - khz passband ripple pr - - 0.005 db stopband attenuation sa 100 - - db group delay ( note 17 ) gd - 39 - 1/fs group delay distortion gd - 0 - s adc digital filter (hpf): frequency response ( note 16 ) ? 3db ? 0.1db fr - - 2.0 13.0 - - hz hz
[AK4621] ms1258-e-01 2011/01 - 10 - adc sharp roll off filter characteristics (fs=192khz) (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; quad speed mode; sdad bit = ?0?) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 16 ) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - - 88.2 89.0 96.0 87.0 - - - khz khz khz khz stopband ( note 16 ) sb 106.0 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 100 - - db group delay ( note 17 ) gd - 36 - 1/fs group delay distortion gd - 0 - s adc digital filter (hpf): frequency response ( note 16 ) ? 3db ? 0.1db fr - - 4.0 26.0 - - hz hz note 16: the passband and stopband frequencies scale w ith fs. each response refers to that of 1khz note 17: the calculated delay time induced by digital filtering. this time is fro m the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc. if the signal is outputted to the sdto pin, group delay is increased 0.5/fs from the above value.
[AK4621] ms1258-e-01 2011/01 - 11 - adc short delay sharp roll off filter characteristics (fs=48khz) (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; normal speed mode; sdad bit = ?1?) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 16 ) ? 0.01db ? 0.1db ? 3.0db ? 6.0db pb 0 - - - - 22.1 23.8 24.4 21.7 - - - khz khz khz khz stopband ( note 16 ) sb 28.2 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 80 - - db group delay ( note 17 ) gd - 14 - 1/fs group delay distortion gd - 0.01 - s adc digital filter (hpf): frequency response ( note 16 ) ? 3db ? 0.1db fr - - 1.0 6.5 - - hz hz adc short delay sharp roll off filter characteristics (fs=96khz) (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; double speed mode; sdad bit = ?1?) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 16 ) ? 0.01db ? 0.1db ? 3.0db ? 6.0db pb 0 - - - - 44.2 47.6 48.9 43.3 - - - khz khz khz khz stopband ( note 16 ) sb 55.9 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 80 - - db group delay ( note 17 ) gd - 14 - 1/fs group delay distortion gd - 0.013 - s adc digital filter (hpf): frequency response ( note 16 ) ? 3db ? 0.1db fr - - 2.0 13.0 - - hz hz adc short delay sharp roll off filter characteristics (fs=192khz) (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; quad speed mode; sdad bit = ?1?) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 16 ) ? 0.01db ? 0.1db ? 3.0db ? 6.0db pb 0 - - - - 81.1 99.9 106.7 76.1 - - - khz khz khz khz stopband ( note 16 ) sb 141.1 - - khz passband ripple pr - - 0.01 db stopband attenuation sa 79 - - db group delay ( note 17 ) gd - 11 - 1/fs group delay distortion gd - 0 - s adc digital filter (hpf): frequency response ( note 16 ) ? 3db ? 0.1db fr - - 4.0 26.0 - - hz hz
[AK4621] ms1258-e-01 2011/01 - 12 - dac sharp roll off filter characteristics (fs = 48khz) (ta = 25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; normal speed mode; dem = off; slow bit = ?0?, sdda bit = ?0?) parameter symbol min typ max units digital filter passband ( note 18 ) -0.04db -6.0db pb 0 - - 24.0 21.8 - khz khz stopband ( note 18 ) sb 26.2 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 70 - - db group delay ( note 19 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 20.0khz - 0.2 - db dac sharp roll off filter characteristics (fs = 96khz) (ta = 25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; double speed mode; dem = off; slow bit = ?0?, sdda bit = ?0?) parameter symbol min typ max units digital filter passband ( note 18 ) -0.04db -6.0db pb 0 - - 48.0 43.5 - khz khz stopband ( note 18 ) sb 52.4 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 70 - - db group delay ( note 19 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 40.0khz - 0.3 - db dac sharp roll off filter characteristics (fs = 192khz) (ta = 25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; quad speed mode; dem = off; slow bit = ?0?, sdda bit = ?0?) parameter symbol min typ max units digital filter passband ( note 18 ) -0.02b -6.0db pb 0 - - 95.9 87.0 - khz khz stopband ( note 18 ) sb 105 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 70 - - db group delay ( note 19 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 80.0khz - +0/-1 - db note 18. the passband and stopband frequencies scale w ith fs. each response refers to that of 1khz. note 19. delay time caused by digital filtering. this time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal.
[AK4621] ms1258-e-01 2011/01 - 13 - dac slow roll off filter characteristics (fs = 48khz) (ta = 25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; normal speed mode; dem = off; slow bit = ?1?, sdda bit = ?0?) parameter symbol min typ max units digital filter passband ( note 18 ) -0.07db -3.0db pb 0 - - 19.8 8.9 - khz khz stopband ( note 18 ) sb 42.6 - - khz passband ripple pr - - 0.07 db stopband attenuation sa 73 - - db group delay ( note 19 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 20.0khz - +0/-5 - db dac slow roll off filter characteristics (fs = 96khz) (ta = 25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; double speed mode; dem = off; slow bit = ?1?, sdda bit = ?0?) parameter symbol min typ max units digital filter passband ( note 18 ) -0.07db -3.0db pb 0 - - 39.5 17.7 - khz khz stopband ( note 18 ) sb 85.1 - - khz passband ripple pr - - 0.07 db stopband attenuation sa 73 - - db group delay ( note 19 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 40.0khz - +0/-4 - db dac slow roll off filter characteristics (fs = 192khz) (ta = 25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; quad speed mode; dem = off; slow bit = ?1?, sdda bit = ?0?) parameter symbol min typ max units digital filter passband ( note 18 ) -0.07db -3.0db pb 0 - - 79.0 35.5 - khz khz stopband ( note 18 ) sb 170.7 - - khz passband ripple pr - - 0.07 db stopband attenuation sa 73 - - db group delay ( note 19 ) gd - 27 - 1/fs digital filter + scf frequency response: 0 80.0khz - +0/-5 - db
[AK4621] ms1258-e-01 2011/01 - 14 - dac short delay sharp roll off filter characteristics (fs = 48khz) (ta = 25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; normal speed mode; dem = off; slow bit = ?0?, sdda bit = ?1?) parameter symbol min typ max units digital filter passband ( note 18 ) -0.04db -6.0db pb 0 - - 24.0 21.8 - khz khz stopband ( note 18 ) sb 26.2 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 70 - - db group delay ( note 19 ) gd - 7 - 1/fs digital filter + scf frequency response: 0 20.0khz - 0.2 - db dac short delay sharp roll off filter characteristics (fs = 96khz) (ta = 25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; double speed mode; dem = off; slow bit = ?0?, sdda bit = ?1?) parameter symbol min typ max units digital filter passband ( note 18 ) -0.03db -6.0db pb 0 - - 48.0 43.5 - khz khz stopband ( note 18 ) sb 52.4 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 70 - - db group delay ( note 19 ) gd - 7 - 1/fs digital filter + scf frequency response: 0 40.0khz - 0.3 - db dac short delay sharp roll off filter characteristics (fs = 192khz) (ta = 25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; quad speed mode; dem = off; slow bit = ?0?, sdda bit = ?1?) parameter symbol min typ max units digital filter passband ( note 18 ) -0.02db -6.0db pb 0 - - 96.2 87.0 - khz khz stopband ( note 18 ) sb 104.9 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 70 - - db group delay ( note 19 ) gd - 7 - 1/fs digital filter + scf frequency response: 0 80.0khz - +0/-1 - db
[AK4621] ms1258-e-01 2011/01 - 15 - dc characteristics (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - tvdd 30%dvdd v v high-level output voltage (iout=-100 a) low-level output voltage (iout=100 a) voh vol dvdd-0.5 - - - - 0.5 v v input leakage current iin - - 10 a switching characteristics (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 3.6v, tvdd=dvdd 5.25v; c l =20pf) parameter symbol min typ max units master clock timing frequency pulse width low pulse width high fclk tclkl tclkh 8.192 0.4/fclk 0.4/fclk - - - 55.296 - - mhz ns ns lrck frequency ( note 20 ) normal speed mode (dfs0=?0?, dfs1=?0?) double speed mode (dfs0=?1?, dfs1=?0?) quad speed mode (dfs0=?0?, dfs1=?1?) duty cycle fsn fsd fsq 32 54 108 45 - - - - 54 108 216 55 khz khz khz % pcm audio interface timing bick period normal speed mode double speed mode quad speed mode bick pulse width low pulse width high lrck edge to bick ? ? ( note 21 ) bick ? ? to lrck edge ( note 21 ) lrck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbck tbck tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 1/128fsn 1/64fsd 1/64fsq 33 33 20 20 - - 20 20 - - - - - - - - - - - - - - - - - - 20 20 - - ns ns ns ns ns ns ns ns ns ns ns note 20. when the normal/double/quad speed modes are switched, the AK4621 must be reset by the pdn pin or rstn bit. note 21. bick rising edge must not occur at the same time as lrck edge.
[AK4621] ms1258-e-01 2011/01 - 16 - parameter symbol min typ max units control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 50 50 150 50 50 - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns reset timing pdn pulse width ( note 22 ) rstad ? ? to sdto valid ( note 23 ) tpd tpdv 150 - - 516 - - ns 1/fs note 22. the AK4621 can be reset by bringing the pdn pin ?l?. note 23. these cycles are the number of lrck rising from rstad bit.
[AK4621] ms1258-e-01 2011/01 - 17 - timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fs lrck vih vil tbck tbckl vih tbckh bick vil figure 2. clock timing lrck bick sdto sdti tblr tlrb tlrs tbsd tsd s tsdh vih vil vih vil 50%tvdd vih vil figure 3. audio interface timing
[AK4621] ms1258-e-01 2011/01 - 18 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh tcsh figure 4. write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh tcss figure 5. write data input timing tpd pdn vil figure 6. power down & reset timing
[AK4621] ms1258-e-01 2011/01 - 19 - operation overview system clock input the AK4621 requires mclk, bick and lrck external clocks. mclk must be synchronized with lrck but the phase is not critical. the AK4621 is automatically placed in pow er-down state when mclk is stopped more than 9.38s during a normal operation (pdn pin =?h?), then the digital output becomes ?0? data and the analog output becomes hi-z. when mclk and lrck are input again, the AK4621 exit power-down state and starts the operation. after exiting system reset (pdn pin =?l? ?h?) at power-up and other situ ations, the AK4621 is in power-down mode until mclk is supplied. as the AK4621 includes the phase detect circuit for lrck, the AK4621 is reset automatically when the synchronization is out of phase by changing the clock frequencies. 1. serial mode (p/s pin= ?l?) as shown in table 1 , table 2 and table 3 , select the mclk frequency by setting cmode, cks1-0 and dfs1-0 bits. these registers are changed when rstad bit = rstda bit = ?0?. dfs1 bit dfs0 bit mode sampling rate 0 0 normal speed 32khz-54khz (default) 0 1 double speed 54khz-108khz 1 0 quad speed 108khz-216khz 1 1 n/a - table 1. sampling speed in serial mode (n/a: not available) cmode bit cks1 bit cks0 bit mclk normal speed (dfs1-0 = ?00?) mclk double speed (dfs1-0 = ?01?) mclk quad speed (dfs1-0 = ?10?) 0 0 0 256fs n/a n/a (default) 0 0 1 512fs 256fs 128fs 0 1 0 1024fs 512fs 256fs 0 1 1 n/a auto setting mode (*) n/a 1 0 0 384fs n/a n/a 1 0 1 768fs 384fs 192fs table 2. master clock frequency in serial mode (?*?; refer to table 3 .) (n/a: not available) the auto setting mode detects mclk/lrck ratio and selects normal/double/quad speed mode automatically ( table 3 ). mclk/lrck ratio mode sampling rate 512 or 768 normal speed 32khz-54khz 256 or 384 double speed 54khz-108khz 128 or 192 quad speed 108khz-216khz table 3. auto setting mode in serial mode (dfs1-0 bits = ?01?, cmode bit = ?0?, cks1-0 bits = ?11?)
[AK4621] ms1258-e-01 2011/01 - 20 - 2. parallel mode (p/s pin= ?h?) as shown in table 4 , table 5 and table 6 , select the mclk frequency with the cks0-1 and dfs0 pins. these pins must be changed when the pdn pin = ?l?. dfs0 pin mode sampling rate l normal speed 32khz-54khz h double speed 54khz-108khz table 4. sampling speed in parallel mode cks1 pin cks0 pin mclk normal speed (dfs0 pin = ?l?) mclk double speed (dfs0 pin = ?h?) l l 256fs n/a l h 512fs 256fs h l 384fs auto setting mode (*) h h 1024fs 512fs table 5. master clock frequency in parallel mode (?*?; refer to table 6 .) (n/a: not available) the auto setting mode detects mclk/lrck ratio and selects normal/double/quad speed mode automatically. ( table 6 ). mclk/lrck ratio mode sampling rate 512 or 768 normal speed 32khz-54khz 256 or 384 double speed 54khz-108khz 128 or 192 quad speed 108khz-216khz table 6. auto setting mode in parallel mode (dfs0 pin = ?h?, cks1 pin = ?h?, cks0 pin = ?l?) mclk (normal speed) fs=44.1khz fs=48khz mclk (double speed) fs=88.2khz fs=96khz 256fs 11.2896mhz 12.288mhz n/a n/a n/a 512fs 22.5792mhz 24.576mhz 256fs 22.5792mhz 24.576mhz 1024fs 45.1584mhz 49.152mhz 512fs 45.1584mhz 49.152mhz 384fs 16.9344mhz 18.432mhz n/a n/a n/a 768fs 33.8688mhz 36.864mhz 384fs 33.8688mhz 36.864mhz mclk (quad speed) fs=176.4khz fs=192khz 128fs 22.5792mhz 24.576mhz 256fs 45.1584mhz 49.152mhz 192fs 33.8688mhz 36.864mhz table 7. master clock frequency example (n/a: not available)
[AK4621] ms1258-e-01 2011/01 - 21 - audio serial interface format five serial modes are supported and selected by the dif2-0 b its in serial mode (two modes by dif pin in parallel mode) as shown in table 8 and table 9 . in all modes the serial data has msb first, 2?s complement format. the sdto is clocked out on the falling edge of bick and the sdti is latche d on the rising edge. mode2 can be used for 20 and 16 msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 sdto sdti lrck bick 0 0 0 0 24bit, msb justified 16bit, lsb justified h/l 48fs 1 0 0 1 24bit, msb justified 20bit, lsb justified h/l 48fs 2 0 1 0 24bit, msb justified 24bit, msb justified h/l 48fs 3 0 1 1 24bit, i 2 s 24bit, i 2 s l/h 48fs 4 1 0 0 24bit, msb justified 24bit, lsb justified h/l 48fs (default) table 8. audio data format (serial mode) mode dif pin sdto sdti lrck bick 2 l 24bit, msb justified 24bit, msb justified h/l 48fs 3 h 24bit, i 2 s 24bit, i 2 s l/h 48fs table 9. audio data format (parallel mode) lrck bick(64fs) sdto ( o ) 0 1 2 19 17 18 20 31 0 1 2 19 17 18 20 31 0 23 1 22 4 23 22 7 6 4 23 sdti(i) 1 14 0 12 11 1 14 0 12 11 sdto-19:msb, 0:lsb; sdti-15:msb, 0:lsb lch data rch data don?t care don?t care 7 6 21 5 3 13 15 30 21 33 5 3 15 13 2 2 figure 7. mode 0 timing lrck bick ( 64fs ) sdto ( o ) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti ( i ) 1 18 0 19 8 7 1 18 0 19 8 7 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb lch data rch data don?t care don?t care 12 11 10 figure 8. mode 1 timing
[AK4621] ms1258-e-01 2011/01 - 22 - lrck bick(64fs) sdto ( o ) 0 1 2 18 19 20 21 22 0 1 2 18 19 20 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 5 4 1 0 32 10 3 2 23 figure 9. mode 2 timing lrck bick(64fs) sdto ( o ) 0 1 2 3 19 20 21 22 0 1 2 3 19 20 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 5 4 1 0 3 2 10 3 2 figure 10. mode 3 timing lrck bick(64fs) sdto ( o ) 0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 12 11 1 22 0 23 12 11 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 11. mode 4 timing
[AK4621] ms1258-e-01 2011/01 - 23 - output volume the AK4621 includes channel independent digital output volumes (datt) with 256 levels and extension digital output volumes (eatt) with 16 levels at linear steps including mute. when exte bit = ?1?, the extension digital output volumes are enabled. these volumes are in front of the dac. if the extension digital output volumes are disabled, the volumes can attenuate the input data from 0db to ? 48db and mute. if the extension digital output volumes are enabled, the volumes can attenuate the input data from 0db to ? 72db and mute. when changing leve ls, transitions are executed via soft changes, eliminating any switching noises. the transiti on time of 1 level, all 256 levels and all 256+16 is shown in table 10 . volume calculating formula is shown in table 13 . transition time sampling speed 1 level 255 to 0 (exte bit = ?0?) 255+15 to 0 (exte bit = ?1?) normal speed mode 4lrck 1020lrck 1080lrck double speed mode 8lrck 2040lrck 2160lrck quad speed mode 16lrck 4080lrck 4320lrck table 10. output digital volume transition time dattl7-0 bits dattr7-0 bits datt_data eattl3-0 bits eattr3-0 bits gain(0db) ffh 255 +0 (default) feh 254 -0.034 fdh 253 -0.068 : : : 02h 2 -42.11 01h 1 -48.13 00h - fh mute table 11. output digital volume setting (exte bit = ?0?) dattl7-0 bits dattr7-0 bits datt_data eattl3-0 bits eattr3-0 bits eatt_data gain(0db) ffh 255 +0 feh 254 -0.034 fdh 253 -0.068 : : : 02h 2 -42.11 01h 1 fh - -48.13 fh 15 -48.72 eh 14 -49.32 : : : 2h 2 -66.22 1h 1 -72.25 00h - 0h - mute note 24. if the volume is set from datt gain to eatt gain or from eatt gain to datt gain, these register must be wrote continuously within 4lrck cycl es in normal speed mode. when the volume setting is not complete within 4lrck cycles, the volume transition may stop. table 12. output digital volume setting (exte bit = ?1?)
[AK4621] ms1258-e-01 2011/01 - 24 - dattl7-0 bits dattr7-0 bits eattl3-0 bits eattr3-0 bits gain(db) ffh : 20 log 10 (datt_data / 255) 01h fh fh : 20 log 10 (eatt_data / 4095) 00h 1h table 13. output digital volume formula overflow detection the adc has a channel independent overflow detection function. this function is enabled in parallel control mode, or when the zos bit = zoe bit = ?0? in serial control mode. ovfl/r pins go to ?h? if each lch/rch analog input overflows (exceeds -0.3dbfs). the output of each ovf l/r pin has same group delay as adc against analog inputs. ovfl/r pin is ?l? for 516/fs (=10.8ms @fs=48khz) after the pdn pin = ? ?, and then overflow detection is enabled. zero detection the dac has a channel-independent zero detect function. the zero detect function is enable d when the zos bit = ?1? and the zoe bit = ?0? in serial control mode. when the input data at both channels is continuously zero for 8192 lrck cycles, the dzf pin of each channel goes to ?h?. the dzf pin of each channel immediately return s to ?l? if the input data of each channel is not zero after dzf ?h?. if the rstda bit is ?0?, the dzf pins of both channels go to ?h?. the dzf pins of both channels return to ?l? in 2~3fs if the input data of each channel is not zero. zero detect function can be disabled by the zoe bit. in this case, the dzf pins of both channels are always ?l?. the dz fb bit can invert the polarity of the dzf pin. digital high pass filter the adc has a digital high pass filter for dc offset cancellati on. the cut-off frequency of the hpf is 1.0hz at fs=48khz. the digital high pass filter cut-off frequency scales with the sampling rate (fs). in parallel mode, the hpf is always enabled. in serial mode, the hpf can control each channel by hpln/hprn bits.
[AK4621] ms1258-e-01 2011/01 - 25 - digital filter the AK4621 has two kinds of digital filter for adc and thr ee kinds of digital filter fo r dac. the outputs of adc and dac can be controlled by using the sdfil pin or sdad/sdda/slow bits. sdfil pin adc dac l short delay sharp roll off filter short delay sharp roll off filter h sharp roll off filter sharp roll off filter table 14. digital filter selection in parallel mode sdad bit adc 0 sharp roll off filter (default) 1 short delay sharp roll off filter table 15. adc digital filter selection in serial mode sdda bit slow bit dac 0 0 sharp roll off filter (default) 0 1 slow roll off filter 1 0 short delay sharp roll off filter 1 1 n/a table 16. dac digital filter selection in serial mode (n/a: not available) de-emphasis filter the dac includes a digital de-emphasis filter (tc=50/15 s for 32khz, 44.1khz or 48khz sampling rates) by an integrated iir filter. setting the dem1-0 bits enab les the de-emphasis filter. this filter is always off in double and quad speed modes. the dem0 pin and dem0 bit are or?d in serial contro l mode. in parallel control mode, the dem1 bit is fixed to ?0? and only the dem0 pin can be controlled (44.1khz or off). no dem1 dem0 mode 0 0 0 44.1khz 1 0 1 off 2 1 0 48khz 3 1 1 32khz (default) table 17. de-emphasis control (normal speed mode)
[AK4621] ms1258-e-01 2011/01 - 26 - soft mute operation soft mute operation is performed in the digital domain of the dac input. when the smute bit goes to ?1?, the output signal is attenuated by ? during att_data att transition time ( table 10 ) from the current att level. when smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if soft mute is cancelled before attenuating to ? after starting the operation, the attenuation is discontinued and returns to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation dzf pin att_level - a out 8192/fs gd gd (1) (2) (3) (4) (1) (2) notes: (1) att_data att transition time ( table 10 ). for example, in normal speed m ode, if the eatt is disabled, this time is 1020lrck cycles (1020/fs). if the eatt is enabled, this time is 1080lrck cycles (1080/fs). (2) analog output corresponding to digital input has group delay (gd). (3) if the soft mute is cancelled before attenuating ? , the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at each cha nnel is continuously zero for 8192 lrck cy cles, the dzf pin of each channel goes to ?h?. the dzf pin immediately returns to ?l? if input data are not zero after going to ?h?. figure 12. soft mute and zero detection
[AK4621] ms1258-e-01 2011/01 - 27 - power down & reset the adc and dac of AK4621 are placed in pow er-down mode by bringing the pdn pin = ?l?. each digital filter is also reset at the same time. the internal register values are initialized by bringing the pdn pin to ?l?. this reset must always be done after power-up. as both control registers of the adc and the dac go to the reset state (rstad bit = rstda bit = ?0?), each register must be cleared af ter executing the reset. in the case of th e adc, an analog initialization cycle starts after exiting the power-down or reset state. the output data (sdto) is available after 516 cycles of lrck clock. this initialization cycle does not affect the dac operation. power down mode can be also controlled by the registers (pwad bit, pwda bit). power supply rstad/rstda bit pwad/pwda bit pwv r bit ad c internal state adc out (digital) datt dac out (analog) dac internal state external mute example clock in mclk, lrck, bick pd reset inita normal pd inita normal ?0? data (3) pd rese t pd normal norm al ffh*1 ffh=>x xh xx h xxh*2 xxh=>yy h y yh hi-z fade fade pd n pin ffh hi-z a dc in (analog) don?t care vcom dac in (digital) ?0?data mu te on ( 7) mute on pd pd in ita normal fade stop hi-z normal mute on (7) yyh*3 yyh=>zzh zzh (1) gd (2) gd (2) gd (2) (1) ?0? data (3) ?0? data (3) (4) (4) (4) gd (2) gd ( 2) gd (2) (6) (6) (6) (6) ( 6) (6) (8) (1) (5) (5) (5) (7) notes: (1) after exiting power down and reset state, th e analog part of adc is initialized (516/fs). (2) digital output corresponding to analog input and anal og input corresponding to digital input have group delay (gd). (3) adc output is ?0? data in power-down state. (4) after exiting power down and reset state, att value fades in/out. *1 when rstda is ?l? and datt value is writte n to ?xxh?, datt value changes from ffh to xxh according to fade operation. *2 when pwda is ?l? and datt value is written to ?yyh?, datt value changes from xxh to yyh according to fade operation. *3 when the external clocks (mclk, sclk, lrck) are stopped and datt value is written to ?zzh?, datt value changes from yyh to zzh according to fade operation. (5) in the power-down mode, the dac output is vcom level. in the reset state, the dac output is floating (hi-z). (6) click noise occurs after rstda bit or pwda bit is changed. (7) mute the analog output externally if the click noise (6) influences system application. (8) when mclk is stopped more than 9.38s, the AK4621 becomes power down mode. then adc output is ?0? data and dac output is floating (hi-z). figure 13. reset & power down sequence in serial mode
[AK4621] ms1258-e-01 2011/01 - 28 - in parallel mode, both adc and dac are powered up when releas ing internal reset state by the pdn pin = ?h?. when the pdn pin is ?l?, after exiting power down mode adc s output ?0? during first 516/fs cycles. dac does not have the initialization cycle and the operation of fade-in. power supply ad c internal state ad c out (digital) dac out (analog) dac internal state external mute example clock in mclk, lrck, bick pd in ita no rmal pd inita no rma l ?0? data (3) pd n orma l nor mal hi-z pd n pin hi-z a dc in (analog) don?t care dac in (digital) ?0?data mute on (6) mute on pd inita normal stop hi-z normal mute on ( 6) (1) gd (2) gd ( 2) gd (2) (1) ?0? data (3) ?0? data (3) gd (2) gd ( 2) gd (2) (5) ( 5) (5) (5) (5) (7) (1) (4) ( 4) (4) (6) pd pd notes: (1) after exiting power down and reset state, the analog part of adc is initialized (516/fs). (2) digital output corresponding to analog input and anal og input corresponding to digital input have group delay (gd). (3) adc output is ?0? data in power-down state. (4) dac output is floating (hi-z) in power-down state. (5) click noise occurs at the rising/falling edge of pdn. (6) mute the analog output externally if the click noise (5) influences system application. (7) when mclk is stopped more than 9.38s, the AK4621 becomes power down mode. then adc output is ?0? data and dac output is floating (hi-z). figure 14. reset & power down sequence in parallel mode
[AK4621] ms1258-e-01 2011/01 - 29 - serial control interface the internal registers may be written by the 3-wire p interface pins: csn, cclk, cd ti. the data on this interface consists of chip address (2bits, c0/1) read/write (1 bit), register address (msb first, 5 bits) and control data (msb first, 8 bits). address and data are clocked in on the rising edge of cclk and data is latched after the 16th rising edge of cclk, following a high-to-low transition of csn. operation of the control serial port may be completely asynchronous with the audio sample rate. the maximum clock speed of the cclk is 5mhz. the chip address is fixed to ?10?. the access to the chip address except for ?10? is invalid. pdn pin = ?l? resets th e registers to their default values. function parallel mode serial mode overflow detection x x dac slow roll off filter - x zero detection - x soft mute - x datt - x hpf off - x 16/20/24 bit lsb justified format of dac - x mclk = 256fs @ quad speed - x de-emphasis: 32khz, 48khz - x table 18. function list (x: available, -: not available) csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdti c1 c0 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w c1-c0: chip address (fixed to ?10?) r/w: read/write (fixed to ?1?:write) a4-a 0: regis ter a ddress d7-d0: control data figure 15. control i/f timing * read command is not supported. * the control data can not be written when the cclk rising edge is 15times or less or 17times or more during csn is ?l?.
[AK4621] ms1258-e-01 2011/01 - 30 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control slow dz fb zoe zos sdda pwvr pwad pwda 01h reset control 0 0 0 sdad 0 0 rstad rstda 02h clock and format control dif2 dif1 dif0 cmode cks1 cks0 dfs1 dfs0 03h deem and volume control smu te hprn hpln 0 0 0 dem1 dem0 04h reserved 0 0 0 0 0 0 0 0 05h reserved 0 0 0 0 0 0 0 0 06h lch datt control dattl7 da ttl6 dattl5 dattl4 dattl3 dattl2 dattl1 dattl0 07h rch datt control dattr7 dattr6 da ttr5 dattr4 dattr3 dattr2 dattr1 dattr0 08h lch extension datt control 0 0 exte 0 eattl3 eattl2 eattl1 eattl0 09h rch extension datt control 0 0 0 0 eattr3 eattr2 eattr1 eattr0 note 25: data must not be writte n to addresses 0ah through 1fh. pdn pin = ?l? resets the registers to their default values. control register setup sequence when the pdn pin goes ?l? to ?h? upon power-up etc., the AK4621 will be ready for normal operation by the sequence below. in this case, all control registers are set to default values and the AK4621 is in the reset state. (1) set the clock mode and the audio data interface mode. (2) cancel the reset state by setting rstad bit or rstda bit to ?1?. refer to reset contorl register (01h). (3) adc output and dac output must be muted externally until canceling each reset state. the clock mode must be changed after setting rstad bit a nd rstda bit to ?0?. at that time, adc outputs and dac outputs must be muted externally.
[AK4621] ms1258-e-01 2011/01 - 31 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control slow dzfb zoe zos sdda pwvr pwad pwda default 0 0 0 0 0 1 1 1 pwda: dac power down 0: power down 1: power up (default) when pwda bit = ?0?, only the dac block is power ed down and the aout becomes hi-z immediately. in this time, all registers are not initialized, and regi ster writings are valid. after exiting power down mode, the oatt fades in/out the setting value of the control register (06h, 07h, 08h, 09h). the analog output must be muted externally as a pop noise ma y occur when entering and exiting this mode. pwad: adc power down 0: power down 1: power up (default) when pwad bit = ?0?, only the adc block is powered-down and the sdto pin becomes ?l? immediately. after exiting power down mode, the adc outputs ?0? during first 516 lrck cycles. pwvr: vref power down 0: power down 1: power up (default) when pwvr bit = ?0?, all blocks are powered down. both adc and dac cannot operate. in this time, all registers are not initialized, and register writings are valid. only the vrfe block can be powered up by setting pwad = pwda bit = ?0? and pwvr bit = ?1?. sdda: dac short delay sharp roll off filter enable ( table 16 ) default: disable zos: zero-detection/ ove rflow-detection control for ovfl/dzfl and ovfr/dzfr pins. 0: overflow detection for adc input (default) 1: zero detection for dac input. zoe: zero-detection / overflow-detection disable 0: enable (default) 1: disable. outputs ?l?. dzfb: inverting enable of dzf 0: dzf goes ?h? at zero detection (default) 1: dzf goes ?l? at zero detection slow: dac slow roll off filter enable ( table 16 ) default: disable
[AK4621] ms1258-e-01 2011/01 - 32 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h reset control 0 0 0 sdad 0 0 rstad rstda default 0 0 0 0 0 0 0 0 rstda: dac reset 0: reset (default) 1: normal operation when rstda bit =?0?, the internal timing of dac is reset and the aout becomes vcom voltage immediately. in this time, all registers are not initia lized, and register writings are valid. after exiting the power down mode, the oatt fades in the setting values of the control register (06h, 07h, 08h, 09h). the analog outputs must be muted extern ally since a pop noise may occur when entering to and exiting from this mode. rstad: adc reset 0: reset (default) 1: normal operation when rstad bit =?0?, the internal timing of adc is reset and the sdto pin becomes ?l? immediately. in this time, all registers are not initialized, and re gister writings are valid. after exiting the power down mode, the adcs output ?0? during first 516 lrck cycles. sdad: adc short delay sharp roll off filter enable ( table 15 ) default: disable addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h clock and format control dif2 dif1 dif0 cmode cks1 cks0 dfs1 dfs0 default 0 1 0 0 0 0 0 0 dfs1-0: sampling speed control ( table 1 ) default: normal speed cmode, cks1-0: master clock frequency select ( table 2 ) default: 256fs dif2-0: audio data interface modes ( table 8 ) 000: mode 0 001: mode 1 010: mode 2 (default) 011: mode 3 100: mode 4 default: 24bit msb justified for both adc and dac
[AK4621] ms1258-e-01 2011/01 - 33 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h deem and volume control smute hprn hpln 0 0 0 dem1 dem0 default 0 0 0 0 0 0 0 1 dem1-0: de-emphasis response ( table 17 ) 00: 44.1khz 01: off (default) 10: 48khz 11: 32khz hpln/rn: left/right channel digital high pass filter disable 0: enable (default) 1: disable smute: dac input soft mute control 0: normal operation (default) 1: dac outputs soft-muted the soft mute is independent of the output att and performed digitally. addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h lch datt control dattl7 dattl6 dattl5 dattl4 da ttl3 dattl2 dattl1 dattl0 07h rch datt control dattr7 dattr6 dattr5 dattr4 dattr3 dattr2 dattr1 dattr0 default 1 1 1 1 1 1 1 1 datt7-0: dac output attenuation level, linear step. ( table 12 , table 13 ) default: 00h (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h lch extension datt control 0 0 exte 0 eattl3 ea ttl2 eattl1 eattl0 09h rch extension datt control 0 0 0 0 eattr3 eattr2 eattr1 eattr0 default 0 0 0 0 1 1 1 1 eatt3-0: dac output extension attenuation level; linear step. ( table 12 , table 13 ) default: fh exte: extension datt enable 0: disable (default) 1: enable
[AK4621] ms1258-e-01 2011/01 - 34 - system design figure 16 shows the system connection diagram. an evaluation boa rd (akd4621) is available for fast evaluation as well as suggestions for peripheral circuitry. + 4.75 5.25v analog supply 10u 10u 0.1u 0.1u 0.1u 0.1u rch out lch out dvdd 5.25v dig ita l s upp ly mode setting/ up audio dsp rch lpf lch lpf vcom ainr+ vref vss1 avdd p/s mclk lrck bick sdto sdti cdti/cks0 cclk/cks1 csn/dif dfs0 sdfi l tvdd dvdd vss2 aoutl- aoutl+ aoutr- aoutr+ pdn dem0 1 2 3 5 6 7 8 9 11 12 13 14 17 18 19 20 21 22 23 26 27 28 29 30 AK4621 + 10 24 25 4 ainr- ainl+ ainl- rch input buffer lch input buffer ovfr/dzfr ovfl/dzfl 15 1 6 3.0 3.6v dig ita l s upp ly notes: - vss1 and vss2 must be connected to the same analog ground plane. - when aout+/- drives some capacitive load, some resistance must be a dded in series between aout+/- and capacitive load. - all digital input pins must not be left floating. figure 16. typical connection diagram
[AK4621] ms1258-e-01 2011/01 - 35 - 1 analog ground digital ground system controller 2 3 4 5 6 7 8 9 10 11 12 30 29 28 27 26 25 24 23 22 21 20 19 13 14 18 17 vcom ain r+ ain r- ain l+ ain l- vref vss1 avdd p/s mclk lrck bic k a outr+ aoutr- a outl+ aoutl- vss2 dvdd tvdd nc dem0 pdn dfs0 csn/dif AK4621 sdto sdti cclk/cks1 cdti/cks0 15 16 ovfr/dzfr ov fl/d zfl figure 17. ground layout 1. ground and power supply decoupling the AK4621 requires careful attention to power supply and grounding layout. to minimize coupling from digital noise, decoupling capacitors must be connected to avdd, dvdd and tvdd respectively. avdd is supplied from the analog supply in the system, and dvdd and tvdd are supplied from the digital supply in the system. power lines of avdd, dvdd and tvdd must be di stributed separately from the point with lo w impedance of regulator etc. the power up sequence is not critical among avdd, dvdd and tvdd. vss1 and vss2 must be connected to one analog ground plane. decoupling capacitors must be as near to the AK4621 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference the differential voltage between vref and vss1 sets the an alog input/output range. the vref pin is normally connected to avdd with a 0.1 f ceramic capacitor. vcom is the signal ground of this chip. a 10 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vc om pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, must be kept away from the vref and vcom pins in order to avoid unwanted coupling into the AK4621. 3. adc output the adc output data format is 2?s complement. the dc offset, including the adc?s own dc offset, is removed by the internal hpf (fc=1.0hz@fs=48khz). the AK4621 samples the analog inputs at 128fs (@normal speed mode), 64fs (@double speed mode) or 32fs (@quad speed mode). the digital filter rejects noise above the stopband except for multiples of 128fs (@normal speed mode), 64fs (@d ouble speed mode) or 32fs (@quad speed mode).
[AK4621] ms1258-e-01 2011/01 - 36 - 4. analog inputs the AK4621 can accept input voltages from vss1 to avdd. the input signal range scales with the vref voltage and is nominally 2.82vpp (vref = 5v), centered around the internal common voltage (about va/2). figure 18 shows an input buffer circuit example. this is a fully differential input buffer circuit with an inverted amplifier (gain: ? 10db). the capacitor of 10nf between ainl+/ ? (ainr+/ ? ) decreases the clock feedthrough noise of the modulator, and it composes a 1st order lpf (fc=360khz) with a 22 resistor before the capacitor. this circuit also has a 1st order lpf (fc=370khz) composed of op-amp. refer to an evaluation board for details. ain+ ain- AK4621 analog in 4.7k 4.7k vp+ vp- njm5532 47 3k 470p 910 22 47 3k 470p 910 22 bias 10n 9.3vpp 2.82vpp 2.82vpp bias 10 0.1 bias 10k 10k va va = 5v vp+ = 15v vp- = -15v figure 18. input buffer example
[AK4621] ms1258-e-01 2011/01 - 37 - 5. analog outputs the analog outputs are fully differential and 2.8vpp (typ. vref = 5v), centered around vcom. the differential outputs are summed externally: vout = (aout+)-(aout-) between aout+ and aout-. if the summing gain is 1, the output range is 5.6vpp (typ. vref = 5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2?s complement. the output voltage is a positiv e full scale for 7fffffh(@24bit) and a negative full scale for 800000h(@24bit). the ideal aout is 0v for 000000h(@24bit). the internal switched-capacitor filter and the external lpf attenuate the noise ge nerated by the delta-sigma modulator beyond the audio passband. figure 19 shows an example of external lpf circuit summing the differential outputs by an op-amp. figure 20 shows an example of differential outputs and lpf circuit example by three op-amps. 4.7k 4.7k 200 4.7k 200 4.7k 330p +vop 330p -vo p aout- aout+ 2.2n ana log ou t AK4621 figure 19. external lpf circuit example 1 (fc = 136khz, q=0.694) frequency response gain 20khz ? 0.01db 40khz ? 0.06db 80khz ? 0.59db table 19. frequency response of external lpf circuit example 1
[AK4621] ms1258-e-01 2011/01 - 38 - 330 100u 180 ao utl - 10k 3. 9n 1. 2k 680 3. 3n 6 4 3 2 7 10u 0.1u 0.1u 10u 10u njm5534d 330 100u 180 aoutl+ 10k 3.9n 1.2k 680 3.3n 6 4 3 2 7 10u 0.1u 0.1u 10u njm5 53 4d 0. 1u + njm5534d 0.1u 10u 100 4 3 2 1.0n 620 620 560 7 + + + + - + - + + + - + + 1.0n lch -15 +15 6 560 figure 20. external lpf circuit example 2 1 st stage 2 nd stage total cut-off frequency 182khz 284khz - q 0.637 - - gain +3.9db -0.88db +3.02db 20khz -0.025 -0.021 -0.046db 40khz -0.106 -0.085 -0.191db frequency response 80khz -0.517 -0.331 -0.848db table 20. frequency response of external lpf circuit example 2
[AK4621] ms1258-e-01 2011/01 - 39 - package d et ail a n ote: dimension "*" does not include mold flash. 0.24 0.06 0.65 *9. 7 0.1 1. 5 m ax a 1 15 16 3 0 30pin vsop (unit: mm) 5. 6 0. 1 7.6 0.2 0.45 0.2 -0. 05 +0. 06 0. 3 0. 17 0.12 m 0.08 1. 2 0. 10 0.10 +0.1 0 -0 .05 0 ~ 8 s package & lead frame material package molding compound: epoxy resin, halogen (bromine and chlorine) free lead frame material: cu alloy lead frame surface treatmen t: solder (pb free) plate
[AK4621] ms1258-e-01 2011/01 - 40 - marking akm AK4621ef xxxxyyyyz yyyy: date code xxxx, z: internal control code
[AK4621] ms1258-e-01 2011/01 - 41 - revision history date ( yy/mm/dd ) revision reason page/line contents 10/12/07 00 first edition 11/01/26 01 description change digital filter names were changed. important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life s upport or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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